The continuing trend of scaling down integrated circuits has motivated the semiconductor industry to consider new techniques for fabricating precise components at sub-micron levels. One important area in semiconductor fabrication is forming the interconnecting structure within the integrated circuit and particularly connections between various levels of metal layers.
As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. In semiconductor devices it may be advantageous to build contact plugs for interlayer connections having high aspect ratio structures, as circuit density will be enhanced. In that light, it becomes critical that the contact structure, particularly were the structure makes physical contact to an underlying conductor, is not damaged during processing.
Forming contact plugs to regions in a semiconductor device are well known. For example, U.S. Pat. No. 6,518,626 describes a method to form a self-aligned contact to a source/drain region of a transistor. The contact is fabricated between transistor gate stacks having sidewall spacers, often formed of an oxide or nitride. The process includes forming an insulating layer, for example an oxide such as BPSG, over the gate stacks and etching through the insulating layer. The sidewall spacers on the gate stack protect the gate stack and allow for lateral margin during the etching process. The etching process, however, does remove some of the sidewall spacer. As the thickness of the spacer decreases with advances in semiconductor designs, removal of a portion of the spacer can create short circuits between the transistor gate stack and the conductive contact plug.
The present invention describes a contact structure and a method to form the contact structure that addresses the above challenges.